The invention is related to signal coupling between wires used on very large scale integration (VLSI) integrated circuit chips. These wires exist on the metal levels above the silicon and are used to connect the devices. There are millions of wires on these integrated circuits. An emerging problem in high performance VLSI digital circuit implementation is maintaining electrical signal integrity on long interconnect nets. Electrical noise can be injected on the interconnect nets and the circuits receiving the signals from several sources. These sources include, but are not limited to: mutual capacitances between the net and its neighbors, mutual inductances between the net and its neighbors, power supply voltage drops at the receiving circuit due to power supply distribution resistance (DC supply noise), and power supply voltage drops at the receiving circuit due to the instantaneous response of the power distribution to changes in the current demand of switching circuits (AC supply noise). These noise sources can superimpose at a specific physical instance and at specific points in time to cause substantial effects on the operation of the digital circuits. These effects can include, but are not limited to: the event of a false switching circuit due to excessive noise at the circuit input, the injection of additional delay to the propagation of the electrical signal along the interconnect, and the injection of additional delay in the operation of the receiving circuit due to a degraded supply voltage or a degraded signal transition rate at the circuit input. The effects of these noise sources on the circuit operation must be accounted for during the design development phase.
During the design development phase preventive measures and compensations must be included to insure that proper operation and expected performance are achieved. To accurately account for the noise sources, all the parameters which influence these effects must be known and quantifiable. These parameters include but are not limited to: the physical geometries of the metal interconnect, the resistance, capacitance and inductance of the interconnect, the signal timing characteristics including switching event time relative to other switching events on the integrated circuit, the signal slew rates, and the receiving circuit noise tolerance.
A difficulty, in practice, is that not all of the parameters are known when the implementation of the nets and circuits is conducted. Another difficulty arises when a hierarchical design methodology is employed for the design development since the modeling of the noise sources and its effects must be considered across the design hierarchies.
Deterministic evaluation of coupling noise voltage is a function of many physical and electrical parameters such as wiring level, widths, spacing, net topologies, drv impedance and slew rates. This evaluation requires electrical modeling and subsequent circuit simulation to assess the sensitivities of these parameters. These sensitivities can be categorized as coupling guidelines that can be directly linked through extracted physical design data. This invention discloses the development and implementation of a technique for using a coupling guideline table early in the design of an integrated circuit when all the parameters generally required for coupling noise voltage calculations are not available. The steps include: creating a flat wire routing map of the integrated circuit, identifying the coupled wire segments on the integrated circuit, tracking wire interconnection patterns on the integrated circuit, deriving electrical parameters for the coupled wire segments, and generating a coupling guideline table with parameters for a plurality of electrical parameters. The parameters in the coupling guideline table are applied to the derived electrical parameters and a report is generated that lists the derived electrical parameters that fail to comply with the parameters in the coupling guideline table.